1 ? fn8247.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyri ght intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. isl90727, isl90728 single volatile 128-tap xdcp digitally controlled potentiometer (xdcp?) the intersil isl90727 and isl90728 are digitally controlled potentiometers (xdcp). each device consists of a resistor array, wiper switches, and a control section. the wiper position is controlled by an i 2 c interface. the potentiometer is implemen ted by a resistor array composed of 127 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the sda and scl inputs. the device can be used in a wide variety of applications including: ? mechanical potentiometer replacement ? transducer adjustment of pressure, temperature, position, chemical, and optical sensors ? rf amplifier biasing ? lcd brightness and contrast adjustment ? gain control and offset adjustment pinout isl90727, isl90728 (6 ld sc-70) top view features ? volatile solid-state potentiometer ?i 2 c serial bus interface ? dcp terminal voltage, 2.7v to 5.5v ?low tempco - rheostat - 45 ppm/ c typical - divider - 15 ppm/ c typical ? 128 wiper tap points - wiper resistance 70 typ at v cc = 3.3v ? low power cmos - active current, 200a max - standby current, 500na max ? available r total values = 50k , 10k ? power on preset to midscale ? direct replacement for ad5247 ? packaging - 6 ld sc-70 ? pb-free plus anneal available (rohs compliant) 1 2 3 6 4 5 vdd gnd scl rh rw sda ordering information part number (see notes 1, 2) part marking r total (k ) temp range (c) package (pb-free) pkg. dwg. # isl90727wie627z-tk anh 10 -40 to +85 6 ld sc-70 p6.049 ISL90727UIE627Z-TK ani 50 -40 to +85 6 ld sc-70 p6.049 isl90728wie627z-tk ccf 10 -40 to +85 6 ld sc-70 p6.049 notes: 1. intersil pb-free plus anneal products empl oy special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020 2. isl90727 has an i 2 c address 5ch and isl90728 has an i 2 c address 7ch data sheet august 2, 2006
2 fn8247.4 august 2, 2006 block diagram pin descriptions pin number symbol description 1 vdd supply voltage 2 gnd ground 3 scl open drain serial clock input 4 sda open drain serial data i/o 5 rw potentiometer wiper terminal 6 rh potentiometer high terminal scl sda gnd rl rw vdd rh i 2 c interface wiper register isl90727, isl90728
3 fn8247.4 august 2, 2006 absolute maximum ratings recommended operating conditions storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v voltage at any dcp pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . class ii, level b at 85c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kv human body model industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v power rating of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. analog specifications over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ (note 3) max unit r total r h to r l resistance w option 10 k u option 50 k r h to r l resistance tolerance -20 +20 % r w wiper resistance v cc = 3.3v @ 25c 85 200 c h /c l /c w potentiometer capacitance 10/10/ 25 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc 0.1 a voltage divider mode inl integral non-linearity -1 0.2 1 lsb (note 4) dnl differential non-linearity monotonic over all tap positions w option -1 0.1 1 lsb (note 4) u option -1 0.1 1 lsb (note 4) zserror (note 5) zero-scale error w option 0 1 3 lsb (note 4) u option 0 0.5 1 fserror (note 6) full-scale error w option -3 -1 0 lsb (note 4) u option -1 -0.5 0 tc v (note 12) ratiometric temperature coefficient dcp register set to 80 hex 15 ppm/c resistor mode rinl (note 10) integral non-linearity dcp register set between 20 hex and ff hex. monotonic over all tap positions -2 0.25 2 mi (note 7) rdnl (note 9) differential non-linearity dcp register set between 20 hex and ff hex. monotonic over all tap positions w option -1 0.1 1 mi (note 7) u option -1 0.1 1 mi (note 7) roffset (note 8) offset w option 0 1 3 mi (note 7) u option 0 0.5 1 mi (note 7) tc r (notes 11, 12) resistance temperature coefficient dcp regi ster set between 20 hex and ff hex 45 ppm/c isl90727, isl90728
4 fn8247.4 august 2, 2006 operating specifications symbol parameter test conditions min typ (note 3) max unit i cc1 v cc supply current (volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and volatile write states only) 200 a i sb v cc current (standby) v cc = +5.5v, i 2 c interface in standby state 500 na i comlkg common-mode leakage voltage at sda pin to gnd or v cc 3a t dcp (note 12) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper change 500 ns v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and i 2 c interface in standby state 3ms serial interface specifications v il sda, and scl input buffer low voltage -0.3 0.3* v cc v v ih sda, and scl input buffer high voltage 0.7* v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05* v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin (note 14) sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition. 1300 ns t low clock low time measured at the 30% of v cc crossing. 1300 ns t high clock high time measured at the 70% of v cc crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v cc . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window. 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc . 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge. both crossing 70% of v cc . 600 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window. 0ns t r (note 14) sda and scl rise time from 30% to 70% of v cc 20 + 0.1 * cb 250 ns isl90727, isl90728
5 fn8247.4 august 2, 2006 sda vs scl timing notes: 3. typical values are for t a = 25c and 3.3v supply voltage. 4. lsb: [v(r w ) 127 ? v(r w ) 0 ] / 127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to ff hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 5. zs error = v(r w ) 0 / lsb. 6. fs error = [v(r w ) 127 ? v cc ] / lsb. 7. mi = | r 127 ? r 0 | / 127. r 127 and r 0 are the measured resistances for the dcp register set to ff hex and 00 hex respectively. roffset = r 0 / mi, when measuring between r w and r l . 8. roffset = r 127 / mi, when measuring between r w and r h . 9. rdnl = (r i ? r i-1 ) / mi - 1, for i = 32 to 127. 10. rinl = [r i ? (mi ? i) ? r 0 ] / mi, for i = 32 to 127. 11. for i = 32 to 127, t = -40c to 85c. max( ) is the maximum value of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 12. this parameter is not 100% tested. 13. v il = 0v, v ih = v cc. 14. these are i 2 c-specific parameters and are not directly tested. however, t hey are used in the device test ing to validate specifications. principles of operation the isl90727 and isl90728 are integrated circuits incorporating one dcp with its associated registers and an i 2 c serial interface providing direct communication between a host and the potentiometer. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of the dcp are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l pins). the r w pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potenti ometer. the position of the wiper terminal within the dcp is controlled by a 7-bit volatile wiper register (wr). the dcp has its own wr. when the wr of the dcp contains all zeroes (wr<6:0> = 00h), its wiper terminal (r w ) is closest to its ?low? terminal (r l ). when the wr of the dcp contains all ones (wr<6:0> = 7fh), its wiper terminal (r w ) is closest to its ?high? terminal (r h ). as the value of the wr increases from all zeroes (00h) to all ones (127 decimal), the wiper moves mono tonically from the position closest to r l to the position closest to r h . at the same time, the resistance between r w and r l increases monotonically, while the resistance between r h and r w decreases monotonically. r l is connected to the gnd pin of the device, so the wiper movement will always be relative to r l . while the isl90727 and isl90728 are being powered up, the wr is reset to 40h (64 decimal), which locates r w roughly at the center between r l and r h . t f (note 14) sda and scl fall time from 70% to 30% of v cc 20 + 0.1 * cb 250 ns cb (note 14) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 14) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2~2.5k . for cb = 40pf, max is about 15~20k 1k operating specifications (continued) symbol parameter test conditions min typ (note 3) max unit t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r tc r max ri () min ri () ? [] max ri () min ri () + [] 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - = isl90727, isl90728
6 fn8247.4 august 2, 2006 the wr and ivr can be read or written directly using the i 2 c serial interface as described in the following sections. i 2 c serial interface the isl90727 and isl90728 support bidirectional bus oriented protocol. the protoc ol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl90727 and isl90728 operate as slave devices in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions (see figure 1). on power-up of the isl90727 and isl90728, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the isl90727 and isl90728 continuously monitor the sda and scl lines for the start condition and do not respond to any command until this condition is met (see figure 1). a start condition is ignored during the power-up sequence and during internal non-volatile write cycles. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 1). an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. duri ng the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 2). the isl90727 and isl90728 respond with an ack after recognition of a start condition followed by a valid identification byte, and once agai n after successful receipt of an address byte. the isl90727 and isl90728 also respond with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte c ontains 0101110 as the seven msbs for the isl90727 and 0111110 as the seven msbs for the isl90728. the lsb in the read/write bit. its value is ?1? for a read operation, and ?0? for a write operation (see table 1) . write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl90727 and isl90728 respond with an ack. at this time, the device enters its standby state (see figure 3). data protection a valid identification byte, addr ess byte, and total number of scl pulses act as a protec tion of both volatile and non-volatile registers. during a write sequence, the data byte is loaded into an internal shift register as it is received. if the address byte is 0, the data byte is transferred to the wiper register (wr) at the falling edge of the scl pulse that loads the last bit (lsb) of the data byte. if an address other than 00h or an invalid slave address is sent, then the device will respond with no ack. read operation a read operation consist of a three byte instruction followed by one or more data bytes (see figure 4). the master initiates the operation issuing the following sequence: a start, the identificatio n byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl90727 and isl90728 respond with an ack. then the isl90727 and isl90728 transmit the data byte as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master then terminates the read operation (issuing a stop condition) following the last bit of the data byte (see figure 4). table 1. identification byte format isl90727 0 1 0 1 1 1 0 r/w isl90728 0 1 1 1 1 1 0 r/w msb lsb isl90727, isl90728
7 fn8247.4 august 2, 2006 sda scl start data data stop stable change data stable figure 1. valid data changes, start and stop conditions figure 2. acknowledge response from receiver sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 3. byte write sequence (isl90727 version shown) s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the isl23711 a c k 0 0 0 11 a c k write signal at sda 0000 0 1 100 0000 signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 00 0 11 s t o p 0 1 0 11 identification byte with r/w =1 a c k s t a r t data byte 110 0 000 00 110 00 figure 4. read sequence (isl90727 version shown) isl90727, isl90728
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8247.4 august 2, 2006 isl90727, isl90728 small outline transistor plastic packages (sc70-6) d e1 e c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 12 3 4 5 6 e1 c l c view c view c l r1 r 4x 1 4x 1 gauge plane l1 seating l2 c plane c base metal with c1 b1 plating b p6.049 6 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.031 0.043 0.80 1.10 - a1 0.000 0.004 0.00 0.10 - a2 0.031 0.039 0.00 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 d 0.073 0.085 1.85 2.15 3 e 0.071 0.094 1.80 2.40 - e1 0.045 0.053 1.15 1.35 3 e 0.0256 ref 0.65 ref - e1 0.0512 ref 1.30 ref - l 0.010 0.018 0.26 0.46 4 l1 0.017 ref. 0.420 ref. l2 0.006 bsc 0.15 bsc n6 65 r 0.004 - 0.10 - r1 0.004 0.010 0.15 0.25 0 o 8 o 0 o 8 o - rev. 2 9/03 notes: 1. dimensioning and tolerance per asme y14.5m-1994. 2. package conforms to eiaj sc70 and jedec mo203ab. 3. dimensions d and e1 are exclusiv e of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the fl at section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millime ter. converted inch dimen- sions are for reference only
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